From: Robin Murphy Date: Wed, 27 May 2015 16:09:34 +0000 (+0100) Subject: iommu/arm-smmu: Fix ATS1* register writes X-Git-Tag: omap-for-v4.3/legacy-v2-signed~171^2^3~4 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=661d962f19c23df492a03f47b583ef6a540d6031;p=pandora-kernel.git iommu/arm-smmu: Fix ATS1* register writes The ATS1* address translation registers only support being written atomically - in SMMUv2 where they are 64 bits wide, 32-bit writes to the lower half are automatically zero-extended, whilst 32-bit writes to the upper half are ignored. Thus, the current logic of performing 64-bit writes as two 32-bit accesses is wrong. Since we already limit IOVAs to 32 bits on 32-bit ARM, the lack of a suitable writeq() implementation there is not an issue, and we only need a little preprocessor ugliness to safely hide the 64-bit case. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Joerg Roedel --- Reading git-diff-tree failed