From: Chon Ming Lee <chon.ming.lee@intel.com>
Date: Tue, 3 Sep 2013 17:30:38 +0000 (+0800)
Subject: drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
X-Git-Tag: v3.13-rc1~76^2~114^2~87
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=65ce4bf5a15fcd4d15898be47795d0550eb2325c;p=pandora-kernel.git

drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

For DP pll settings, there is only two golden configs.  Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.

v2: Rework on the intel_limit compiler warning. (Jani)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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