From: Florian Fainelli <florian@openwrt.org>
Date: Tue, 31 Jan 2012 17:18:45 +0000 (+0100)
Subject: MIPS: introduce CPU_R4K_CACHE_TLB
X-Git-Tag: v3.7-rc1~77^2^2~7
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=62cedc4fde2d15b08e4502aa3fb2d9d798f3ccd8;p=pandora-kernel.git

MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
---

Reading git-diff-tree failed