From: Steven J. Hill <sjhill@mips.com>
Date: Wed, 29 Aug 2012 04:20:08 +0000 (-0500)
Subject: MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
X-Git-Tag: v3.7-rc1~77^2~5^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=625c0a21700bdb90844d926a1508a17a77e369c9;p=pandora-kernel.git

MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
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