From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Thu, 16 Oct 2014 18:27:34 +0000 (+0300)
Subject: drm/i915: Wait for PHY port ready before link training on VLV/CHV
X-Git-Tag: omap-for-v3.20/drop-legacy-3517~77^2~64^2~114
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=61234fa5e5232c35f87d44d9d596af4b10eac255;p=pandora-kernel.git

drm/i915: Wait for PHY port ready before link training on VLV/CHV

There's no point in checking if the data lanes came out of reset after
link training. If the data lanes aren't ready link training will fail
anyway.

Suggested-by: Todd Previte <tprevite@gmail.com>
Cc: Todd Previte <tprevite@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Acked-by: Todd Previte <tprevite@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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