From: Felix Fietkau Date: Mon, 29 Sep 2014 18:45:42 +0000 (+0200) Subject: ath9k_hw: fix PLL clock initialization for newer SoC X-Git-Tag: fixes-against-v3.18-rc2~144^2~39^2~27 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5fb9b1b949ce9b829e7e8f799cc85e91527213bd;p=pandora-kernel.git ath9k_hw: fix PLL clock initialization for newer SoC On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL register changed. This currently breaks at least 5/10 MHz operation. AR933x uses the old layout. It might also have been causing other stability issues because of the different location of the PLL_BYPASS bit which needs to be set during PLL clock initialization. This patch also removes more instances of hardcoded register values in favor of properly computed ones with the PLL_BYPASS bit added. Reported-by: Lorenzo Bianconi Signed-off-by: Felix Fietkau Signed-off-by: John W. Linville --- Reading git-diff-tree failed