From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Fri, 27 Jun 2014 23:04:08 +0000 (+0300)
Subject: drm/i915: Add chv cmnlane power wells
X-Git-Tag: fixes-against-v3.18-rc2~73^2~78^2~53
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5d6f7ea752228788eddce0b9e268fa1f0eabdd7f;p=pandora-kernel.git

drm/i915: Add chv cmnlane power wells

CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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