From: Graf Yang <graf.yang@analog.com>
Date: Fri, 10 Jul 2009 11:34:51 +0000 (+0000)
Subject: Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
X-Git-Tag: v2.6.31-rc4~22^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5bc6e3cfe6db5f33c60f042a9ba203431f334756;p=pandora-kernel.git

Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions

The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions.  Any code that attempted to use these would wrongly crash due to
a CPLB miss.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---

Reading git-diff-tree failed