From: Markos Chandras Date: Tue, 2 Dec 2014 09:46:19 +0000 (+0000) Subject: MIPS: Add LLB bit and related feature for the Config 5 CP0 register X-Git-Tag: omap-for-v4.1/prcm-dts-mfd-syscon-fix~5^2~26^2~9 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5aed9da128be27275b0892fb413f3a0af64e00a6;p=pandora-kernel.git MIPS: Add LLB bit and related feature for the Config 5 CP0 register The LLBIT (bit 4) in the Config5 CP0 register indicates the software availability of the Load-Linked bit. This bit is only set by hardware and it has the following meaning: 0: LLB functionality is not supported 1: LLB functionality is supported. The following feature are also supported: - ERETNC instruction. Similar to ERET but it does not clear the LLB bit in the LLAddr register. - CP0 LLAddr/LLB bit must be set - LLbit is software accessible through the LLAddr[0] This will be used later on to emulate R2 LL/SC instructions. Signed-off-by: Markos Chandras --- Reading git-diff-tree failed