From: Matt Burtch <matt@grid-net.com>
Date: Mon, 17 Oct 2011 16:25:45 +0000 (-0700)
Subject: ARM: i.MX28: shift frac value in _CLK_SET_RATE
X-Git-Tag: v3.2-rc1~99^2~3^2~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=590842f90984f96a3da6d8b59447dfa1d186d01e;p=pandora-kernel.git

ARM: i.MX28: shift frac value in _CLK_SET_RATE

Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to
reset the clock divider for the SSP0 parent clock, in this case
IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but
when the new frac value is written the value isn't shifted up to write
the correct bit-field.  This results in IO0FRAC being set to 0 and
CPUFRAC being corrupted.

This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0
and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1.

Tested on custom i.MX28 board with SSP0 SPI driver.

Signed-off-by: Matt Burtch <matt@grid-net.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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