From: Gaurav K Singh <gaurav.k.singh@intel.com>
Date: Thu, 4 Dec 2014 05:28:52 +0000 (+0530)
Subject: drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
X-Git-Tag: fixes-v4.0-rc1~91^2~43^2~68
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=58cf8887c94d8dfe42206af7de57163ce0f46cf2;p=pandora-kernel.git

drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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