From: Kisoo Yu <ksoo.yu@samsung.com>
Date: Tue, 24 Apr 2012 21:54:15 +0000 (-0700)
Subject: ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
X-Git-Tag: v3.5-rc1~68^2~1^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=57b317f912b3f4b05c834818c73d7c8ea22642f7;p=pandora-kernel.git

ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---

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