From: Trent Piepho Date: Wed, 17 Dec 2008 19:43:26 +0000 (-0800) Subject: powerpc/fsl-pci: Set relaxed ordering on prefetchable ranges X-Git-Tag: v2.6.29-rc2~76^2~17^2~2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=565f37642c78754a85efe6c20a4a15e18ed21f07;p=pandora-kernel.git powerpc/fsl-pci: Set relaxed ordering on prefetchable ranges Provides a small speedup when accessing pefetchable ranges. To indicate that a memory range is prefetchable, mark it in the dts file with 42000000 instead of 02000000. A powepc pci_controller is allowed three memory ranges, any of which may be prefetchable. However, the PCI-PCI bridge configuration space only has one field for "non-prefetchable memory behind bridge", which has a 32 bit address, and one field for "prefetchable memory behind bridge", which may have a 64 bit address. These are PCI bus addresses, not CPU physical addresses. So really you're only allowed one memory range of each type. And if you want the range at a PCI address above 32 bits you must make it prefetchable. Signed-off-by: Trent Piepho Signed-off-by: Kumar Gala --- Reading git-diff-tree failed