From: Viresh Kumar <viresh.kumar@st.com>
Date: Tue, 10 Apr 2012 03:32:35 +0000 (+0530)
Subject: SPEAr: clk: Add VCO-PLL Synthesizer clock
X-Git-Tag: v3.5-rc1~71^2~2^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=55b8fd4f428501b0f35d62b8313311fd9863c188;p=pandora-kernel.git

SPEAr: clk: Add VCO-PLL Synthesizer clock

All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
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