From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Apr 2014 16:33:13 +0000 (-0500)
Subject: bus: omap_l3_noc: Add DRA7 interconnect error data
X-Git-Tag: omap-for-v3.16/l3-noc-signed~1
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad;p=pandora-kernel.git

bus: omap_l3_noc: Add DRA7 interconnect error data

DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
     <0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
     <0x45000000 0x1000> is clk3

Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
---

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