From: Tingting Meng <tingting.meng@altera.com>
Date: Tue, 15 Apr 2025 01:55:35 +0000 (+0800)
Subject: arm: dts: agilex5: Update CCU configuration
X-Git-Tag: v2025.07-rc1~42^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=52891fda68977e321043c2c4e04f6f3d55352726;p=pandora-u-boot.git

arm: dts: agilex5: Update CCU configuration

Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
---

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index b34af85c58d..874e71b5ca4 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -208,7 +208,8 @@
 				intel,offset-settings =
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
-					<0x00000300 0x00000003 0x00000003>;
+					<0x00000300 0x00000003 0x00000003>,
+					<0x00000308 0x00000004 0x0000001F>;
 				bootph-all;
 			};
 
@@ -218,7 +219,8 @@
 				intel,offset-settings =
 					/* DMIUSMCTCR */
 					<0x00000300 0x00000001 0x00000003>,
-					<0x00000300 0x00000003 0x00000003>;
+					<0x00000300 0x00000003 0x00000003>,
+					<0x00000308 0x00000004 0x0000001F>;
 				bootph-all;
 			};
 		};