From: Christian König <christian.koenig@amd.com>
Date: Thu, 18 Apr 2013 13:25:58 +0000 (+0200)
Subject: drm/radeon: put UVD PLLs in bypass mode
X-Git-Tag: omap-for-v3.10/dt-fixes-for-merge-window~55^2~35^2~16
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4ed108352d9b60a723a5071ed05e722826c2b72f;p=pandora-kernel.git

drm/radeon: put UVD PLLs in bypass mode

Just power down the PLL when we get a VCLK or DCLK of zero.
Enabling the bypass mode early should also allow us to
switch UVD clocks on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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