From: Ian Abbott <abbotti@mev.co.uk>
Date: Thu, 3 Jul 2014 13:46:39 +0000 (+0100)
Subject: video: da8xx-fb: preserve display width when changing HSYNC
X-Git-Tag: fix-v3.17-io-chain-v3~15^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4d4e2c003bd6c6bdd85080bd096d54d5d251defa;p=pandora-kernel.git

video: da8xx-fb: preserve display width when changing HSYNC

When looking at this driver for a client, I noticed the code that
configures the HSYNC pulse clobbers the display width in the same
register.  It only preserves the MS part of the width in bit 3 and zeros
the LS part of the width in bits 9 to 4.  This doesn't matter during
initialization as the width is configured afterwards, but subsequent use
of the FBIPUT_HSYNC ioctl would clobber the width.

Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the
horizontal sync.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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