From: Thierry Reding <treding@nvidia.com>
Date: Fri, 4 Apr 2014 13:55:15 +0000 (+0200)
Subject: clk: tegra: Fix enabling of PLLE
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~128^2^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4ccc402ece35695dd2884ec0b652d52ae0230f13;p=pandora-kernel.git

clk: tegra: Fix enabling of PLLE

When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
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