From: Shinya Kuribayashi Date: Fri, 6 Nov 2009 12:48:12 +0000 (+0900) Subject: i2c-designware: Set Tx/Rx FIFO threshold levels X-Git-Tag: v2.6.33-rc1~339^2~15 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4cb6d1d6da471d795320cc4a933ce60f415dd1f6;p=pandora-kernel.git i2c-designware: Set Tx/Rx FIFO threshold levels As a hardware feature, DW I2C core generates a STOP condition whenever the Tx FIFO becomes empty (strictly speaking, whenever the last byte in the Tx FIFO is sent out), even if we have more bytes to be written. In other words, we must never make "Tx FIFO underrun" happen during a transaction, except for the last byte. For the safety's sake, we'd make TX_EMPTY interrupt get triggered every time one byte is processed. The Rx FIFO threshold needs to be set as well. Signed-off-by: Shinya Kuribayashi Acked-by: Baruch Siach Signed-off-by: Ben Dooks --- Reading git-diff-tree failed