From: Patrice Chotard Date: Tue, 1 Apr 2025 13:14:08 +0000 (+0200) Subject: clk: stm32mp1: fix DSI clock setting X-Git-Tag: v2025.07-rc1~11^2~27 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4cb12871b20ed2d071b5e4cfa03de2d8fe707d23;p=pandora-u-boot.git clk: stm32mp1: fix DSI clock setting DSI is the peripheral clock, while DSI_K is an internal kernel clock. Even though they get the same register and same bit set to be gated, resulting in the same behavior. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Patrice Chotard --- diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 4044edfb768..9cb69a01f7f 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -551,6 +551,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q), STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI, _DSI_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),