From: Damien Lespiau <damien.lespiau@intel.com>
Date: Fri, 6 Mar 2015 18:50:48 +0000 (+0000)
Subject: drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
X-Git-Tag: omap-for-v4.1/fixes-rc1~82^2~24^2~52
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4c6c03be125e9d8477c2d8ef3c3280270956b1fe;p=pandora-kernel.git

drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask

While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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