From: Andrew Lunn <andrew@lunn.ch>
Date: Sat, 22 Feb 2014 19:14:52 +0000 (+0100)
Subject: ARM: MM: Add DT binding for Feroceon L2 cache
X-Git-Tag: v3.15-rc1~79^2~14^2^2~9
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4b8f7a11c9fb680895e5079788653a59d6bdde16;p=pandora-kernel.git

ARM: MM: Add DT binding for Feroceon L2 cache

Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
---

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