From: Alexander Duyck <alexander.h.duyck@intel.com>
Date: Fri, 22 Jun 2012 06:46:33 +0000 (+0000)
Subject: ixgbe: Update the logic for ixgbe_cache_ring_dcb and DCB RSS configuration
X-Git-Tag: v3.6-rc1~125^2~118^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4ae63730bb420610cb99ed152d6daa35236cc9e9;p=pandora-kernel.git

ixgbe: Update the logic for ixgbe_cache_ring_dcb and DCB RSS configuration

This change cleans up some of the logic in an attempt to try and simplify
things for how we are configuring DCB w/ RSS.

In this patch I basically did 3 things.  I updated the logic for getting
the first register index.  I applied the fact that all TCs get the same
number of queues to simplify the looping logic in caching the DCB ring
register.  Finally I updated how we configure the RQTC register to match
the fact that all TCs are assigned the same number of queues.

Cc: John Fastabend <john.r.fastabend@intel.com>
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---

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