From: Axel Lin <axel.lin@gmail.com>
Date: Mon, 24 Oct 2011 03:32:41 +0000 (+0800)
Subject: ASoC: wm8940: Fix setting PLL Output clock division ratio
X-Git-Tag: v3.3-rc1~14^2~414
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3;p=pandora-kernel.git

ASoC: wm8940: Fix setting PLL Output clock division ratio

According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---

Reading git-diff-tree failed