From: Paul Walmsley Date: Tue, 12 May 2009 23:26:32 +0000 (-0600) Subject: OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz X-Git-Tag: v2.6.31-rc1~344^2~23^2~18^2~3 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4519c2bf433b97d091635eb51e4ba8ffa1c84d62;p=pandora-kernel.git OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley --- Reading git-diff-tree failed