From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 9 Aug 2013 14:49:29 +0000 (+0200)
Subject: ARM: tegra: Fix Beaver's PCIe lane configuration
X-Git-Tag: v3.12-rc1~116^2~9^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=44fefab459cfb78c446a8b7cc4bbf622d5b97396;p=pandora-kernel.git

ARM: tegra: Fix Beaver's PCIe lane configuration

Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.

Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---

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