From: Shawn Guo Date: Thu, 31 Oct 2013 01:46:17 +0000 (+0800) Subject: ARM: imx: set up pllv3 POWER and BYPASS sequentially X-Git-Tag: v3.13-rc1~55^2~8^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=43c9b9e8a4c64b1dd3026ab233703a4321ac6d7c;p=pandora-kernel.git ARM: imx: set up pllv3 POWER and BYPASS sequentially Currently, POWER and BYPASS bits are set up in a single write to pllv3 register. This causes problem occasionally from the IPU/HDMI testing. Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS sequentially. Signed-off-by: Shawn Guo --- Reading git-diff-tree failed