From: Javi Merino <javi.merino@arm.com>
Date: Wed, 16 Nov 2011 11:36:39 +0000 (+0100)
Subject: ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field
X-Git-Tag: v3.3-rc5~26^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=4272f98a1ae81709fc5c804c33c044064e419cd9;p=pandora-kernel.git

ARM: 7164/3: PL330: Fix the size of the dst_cache_ctrl field

dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit
field in the Channel Control Register (see Table 3-21 of the DMA-330
Technical Reference Manual) and should be programmed as such.

Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com>

Signed-off-by: Javi Merino <javi.merino@arm.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

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