From: Nicolas Pitre <nico@cam.org>
Date: Fri, 19 Sep 2008 02:55:47 +0000 (-0400)
Subject: [ARM] xsc3: add highmem support to L2 cache handling code
X-Git-Tag: v2.6.30-rc1~636^2~16^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3902a15e784e9b1efa8e6ad246489c609e0ef880;p=pandora-kernel.git

[ARM] xsc3: add highmem support to L2 cache handling code

On xsc3, L2 cache ops are possible only on virtual addresses.  The code
is rearranged so to have a linear progression requiring the least amount
of pte setups in the highmem case.  To protect the virtual mapping so
created, interrupts must be disabled currently up to a page worth of
address range.

The interrupt disabling is done in a way to minimize the overhead within
the inner loop.  The alternative would consist in separate code for
the highmem and non highmem compilation which is less preferable.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
---

Reading git-diff-tree failed