From: Gavin Shan Date: Mon, 4 Nov 2013 08:32:47 +0000 (+0800) Subject: powerpc/powernv: Reserve the correct PE number X-Git-Tag: omap-for-v3.13/fixes-for-merge-window-take2~19^2~1 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=36954dc78d8a1dcd4780cf4bd0fc6292791821b9;p=pandora-kernel.git powerpc/powernv: Reserve the correct PE number We're assigning PE numbers after the completion of PCI probe. During the PCI probe, we had PE#0 as the super container to encompass all PCI devices. However, that's inappropriate since PELTM has ascending order of priority on search on P7IOC. So we need PE#127 takes the role that PE#0 has previously. For PHB3, we still have PE#0 as the reserved PE. The patch supposes that the underly firmware has built the RID to PE# mapping after resetting IODA tables: all PELTM entries except last one has invalid mapping on P7IOC, but all RTEs have binding to PE#0. The reserved PE# is being exported by firmware by device tree. Signed-off-by: Gavin Shan Signed-off-by: Benjamin Herrenschmidt --- Reading git-diff-tree failed