From: Kelvin Cheung Date: Wed, 20 Jun 2012 19:05:32 +0000 (+0100) Subject: MIPS: Add CPU support for Loongson1B X-Git-Tag: v3.6-rc1~49^2^8~2 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2fa36399e63c911134f28b6878aada9b395c4209;p=pandora-kernel.git MIPS: Add CPU support for Loongson1B Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Kelvin Cheung Cc: To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung Patchwork: https://patchwork.linux-mips.org/patch/3976/ Signed-off-by: Ralf Baechle --- Reading git-diff-tree failed