From: Joseph Lo <josephl@nvidia.com>
Date: Wed, 3 Jul 2013 09:50:39 +0000 (+0800)
Subject: ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15
X-Git-Tag: v3.12-rc1~115^2~13^2~20
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2f5aaa3d2703256d37ae75818c495783d4ad0543;p=pandora-kernel.git

ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15

When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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