From: Rafał Miłecki <zajec5@gmail.com>
Date: Fri, 16 May 2014 09:10:29 +0000 (+0200)
Subject: drm/radeon/hdmi: DCE3: clean ACR control
X-Git-Tag: omap-for-v3.16/fixes-against-rc1~44^2~37^2~24
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2e93cac90c4b063c8732deb727a192dea1119640;p=pandora-kernel.git

drm/radeon/hdmi: DCE3: clean ACR control

What initially seemed to be a typo in fglrx (using register 0x740c
instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and
CRC registers swapped which explains why we needed
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

This has been tested for possible regressions on DCE3 HD3470 (RV620).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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