From: Michael Williamson <michael.williamson@criticallink.com>
Date: Fri, 20 May 2011 14:26:06 +0000 (-0400)
Subject: audio: tlv320aic26: fix PLL register configuration
X-Git-Tag: v3.0-rc7~11^2^2~3^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2aba76f014a7b56ab4fe75845c5fd57b5590acc2;p=pandora-kernel.git

audio: tlv320aic26: fix PLL register configuration

The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz.  Use the clock value provided by the DAI_OPS
API for the calculation.

Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.

Signed-off-by: Michael Williamson <michael.williamson@criticallink.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>
---

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