From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Date: Thu, 27 Sep 2012 13:43:06 +0000 (+0530)
Subject: drm/i915: Enable DisplayPort in Valleyview
X-Git-Tag: v3.8-rc1~82^2~192^2~216
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8;p=pandora-kernel.git

drm/i915: Enable DisplayPort in Valleyview

In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.

Cleaned up DPLL calculations for Valleyview to support multi display
configurations.

v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: drop spurious whitespace changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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