From: Kever Yang <kever.yang@rock-chips.com>
Date: Thu, 13 Nov 2014 08:11:49 +0000 (+0800)
Subject: clk: rockchip: fix clock select order for rk3288 usbphy480m_src
X-Git-Tag: omap-for-v3.19/fixes-rc1~9^2~23^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=29e94468516cdf191ec839ee39f79e011817276d;p=pandora-kernel.git

clk: rockchip: fix clock select order for rk3288 usbphy480m_src

According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

Reading git-diff-tree failed