From: Will Deacon <will.deacon@arm.com>
Date: Mon, 3 Oct 2011 17:30:53 +0000 (+0100)
Subject: ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
X-Git-Tag: v3.1-rc10~2^2~2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=29a541f6c1f6e4a85628bb86071b9e72c9f8be2c;p=pandora-kernel.git

ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9

Using COHERENT_LINE_{MISS,HIT} for cache misses and references
respectively is completely wrong. Instead, use the L1D events which
are a better and more useful approximation despite ignoring instruction
traffic.

Reported-by: Alasdair Grant <alasdair.grant@arm.com>
Reported-by: Matt Horsnell <matt.horsnell@arm.com>
Reported-by: Michael Williams <michael.williams@arm.com>
Cc: stable@kernel.org
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---

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