From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Wed, 24 Jun 2015 19:00:06 +0000 (+0300)
Subject: drm/i915: Use the memory latency based WM computation on VLV too
X-Git-Tag: omap-for-v4.3/fixes-rc1~89^2~36^2~132
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=26e1fe4fbd4c15919f8cfa9440d70eca5a457ba3;p=pandora-kernel.git

drm/i915: Use the memory latency based WM computation on VLV too

In order to get decnet memory self refresh residency on VLV, flip it
over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS
so it's a bit simpler.

I'm not sure the currently memory latency used for CHV is really
appropriate for VLV. Some further testing will probably be needed to
figure that out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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