From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date: Wed, 27 Nov 2013 10:07:53 +0000 (+0000)
Subject: MIPS: Add support for interAptiv cores
X-Git-Tag: v3.14-rc1~37^2~88
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=26ab96dfa9f98d74ef38efbe830d356547a292c1;p=pandora-kernel.git

MIPS: Add support for interAptiv cores

The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
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