From: Stephen Warren <swarren@nvidia.com>
Date: Thu, 26 Apr 2012 17:19:03 +0000 (-0600)
Subject: ARM: dt: tegra seaboard: fix I2C2 SCL rate
X-Git-Tag: v3.5-rc1~69^2~4^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=22bd1f7ef40a1c0f2ba796ba7cd80013adcb835d;p=pandora-kernel.git

ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
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