From: Santhosh Kumar K <s-k6@ti.com>
Date: Wed, 26 Feb 2025 06:39:23 +0000 (+0530)
Subject: arm: dts: k3-am62p: Update DDR Configurations
X-Git-Tag: v2025.07-rc1~18^2~50^2
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=226f16e40650e6c8a0b49ba3f29ab3b0393df19d;p=pandora-u-boot.git

arm: dts: k3-am62p: Update DDR Configurations

Update the DDR Configurations for AM62Px SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
---

diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
index f6643520153..c7e33ba50b9 100644
--- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
+++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02
- * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time)
+ * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1600MHz
  * Density (per channel): 16Gb
@@ -941,7 +941,7 @@
 #define DDRSS_PHY_64_DATA 0x00000000
 #define DDRSS_PHY_65_DATA 0x00000000
 #define DDRSS_PHY_66_DATA 0x00000000
-#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_67_DATA 0x00000104
 #define DDRSS_PHY_68_DATA 0x00000000
 #define DDRSS_PHY_69_DATA 0x00000000
 #define DDRSS_PHY_70_DATA 0x00000000
@@ -1197,7 +1197,7 @@
 #define DDRSS_PHY_320_DATA 0x00000000
 #define DDRSS_PHY_321_DATA 0x00000000
 #define DDRSS_PHY_322_DATA 0x00000000
-#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_323_DATA 0x00000104
 #define DDRSS_PHY_324_DATA 0x00000000
 #define DDRSS_PHY_325_DATA 0x00000000
 #define DDRSS_PHY_326_DATA 0x00000000
@@ -1453,7 +1453,7 @@
 #define DDRSS_PHY_576_DATA 0x00000000
 #define DDRSS_PHY_577_DATA 0x00000000
 #define DDRSS_PHY_578_DATA 0x00000000
-#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_579_DATA 0x00000104
 #define DDRSS_PHY_580_DATA 0x00000000
 #define DDRSS_PHY_581_DATA 0x00000000
 #define DDRSS_PHY_582_DATA 0x00000000
@@ -1709,7 +1709,7 @@
 #define DDRSS_PHY_832_DATA 0x00000000
 #define DDRSS_PHY_833_DATA 0x00000000
 #define DDRSS_PHY_834_DATA 0x00000000
-#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_835_DATA 0x00000104
 #define DDRSS_PHY_836_DATA 0x00000000
 #define DDRSS_PHY_837_DATA 0x00000000
 #define DDRSS_PHY_838_DATA 0x00000000