From: Maciej W. Rozycki <macro@linux-mips.org>
Date: Wed, 17 Oct 2007 10:51:39 +0000 (+0100)
Subject: [MIPS] c-r3k: Implement flush_cache_range()
X-Git-Tag: v2.6.24-rc2~95^2~6
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=21b2aecaae3a46a13dbe775639e7d060bec033bd;p=pandora-kernel.git

[MIPS] c-r3k: Implement flush_cache_range()

Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache.  Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.

While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

Reading git-diff-tree failed