From: Alif Zakuan Yuslaimi Date: Mon, 4 Aug 2025 01:24:40 +0000 (-0700) Subject: arm: socfpga: Define the usage of boot scratch cold reg 8 X-Git-Tag: v2025.10-rc2~3^2~21 X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=209d53eb1b486776dd1a7ad7f8611083fff7ad26;p=pandora-u-boot.git arm: socfpga: Define the usage of boot scratch cold reg 8 The boot scratch cold reg 8 is shared between DBE, DDR init progress update and Linux EDAC. This patch defines how the bits are used by respective features above and their macro names used in U-Boot. Signed-off-by: Tien Fong Chee Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c2ca0a50e35..8e12aeec011 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -141,6 +141,19 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)