From: Tingting Meng <tingting.meng@altera.com>
Date: Mon, 10 Mar 2025 07:29:41 +0000 (+0800)
Subject: arm: socfpga: agilex5: Add MMU mapping region
X-Git-Tag: v2025.07-rc1~42^2~4
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1f8d5085e985884ae1c82254d6e1af231f9d9e8b;p=pandora-u-boot.git

arm: socfpga: agilex5: Add MMU mapping region

MMU mapping regions were added for the second and third DDR memory banks.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>
---

diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index b8e40d9a788..1dc44ab4797 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -57,6 +57,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = {
 		.size	= 0x80000000UL,
 		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* MEM 30GB */
+		.virt	= 0x880000000UL,
+		.phys	= 0x880000000UL,
+		.size	= 0x780000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* MEM 480GB */
+		.virt	= 0x8800000000UL,
+		.phys	= 0x8800000000UL,
+		.size	= 0x7800000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
 	}, {
 		/* List terminator */
 	},