From: Russ Anderson <rja@sgi.com>
Date: Wed, 31 Oct 2007 16:10:38 +0000 (-0500)
Subject: [IA64] Disable/re-enable CPE interrupts on Altix
X-Git-Tag: v2.6.24-rc3~169^2~5
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1f3b6045f783ee394076ad6dba2d72ecaaecd243;p=pandora-kernel.git

[IA64] Disable/re-enable CPE interrupts on Altix

When the CPE handler encounters too many CPEs (such as a solid single
bit memory error), it sets up a polling timer and disables the CPE
interrupt (to avoid excessive overhead logging the stream of single
bit errors).  disable_irq_nosync() calls chip->disable() to provide
a chipset specifiec interface for disabling the interrupt.  This patch
adds the Altix specific support to disable and re-enable the CPE interrupt.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
---

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