From: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Thu, 29 Nov 2012 14:59:32 +0000 (+0100)
Subject: drm/i915: rip out pre-production ilk cpu edp w/a
X-Git-Tag: v3.9-rc1~83^2~40^2~38
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=1ce17038093f02e708e5816f645bbec63aff8bd2;p=pandora-kernel.git

drm/i915: rip out pre-production ilk cpu edp w/a

While reading docs I've noticed that this special workaround to select
the 1.6 GHz DP clock only applies to pre-production ilk machines.
Since the registers we're touching here are rather undocumented and
might be harmful on later chips, rip it out.

For the Bspec reference of this w/a look in "vol4g CPU Display
Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A
Control Register", "DP_PLL_Frequency_Select".

v2: Keep a debug message as a hint in case something regresses.
Requested by Chris Wilson.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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