From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date: Mon, 29 Oct 2012 14:59:26 +0000 (+0200)
Subject: drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
X-Git-Tag: v3.8-rc1~82^2~192^2~78
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=17f10fdc010254b8e9c0f1779abdaaee4757cabf;p=pandora-kernel.git

drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths

Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:

commit 27c1cbd06a7620b354cbb363834f3bb8df4f410d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Apr 9 13:59:46 2012 +0100

    drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

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