From: Zhenyu Wang <zhenyuw@linux.intel.com>
Date: Tue, 2 Nov 2010 09:30:46 +0000 (+0800)
Subject: agp/intel: fix cache control for sandybridge
X-Git-Tag: v2.6.37-rc2~33^2~23^2~3
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c;p=pandora-kernel.git

agp/intel: fix cache control for sandybridge

This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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