From: Dan Williams <dan.j.williams@intel.com>
Date: Wed, 9 Sep 2009 00:53:04 +0000 (-0700)
Subject: ioat2,3: cacheline align software descriptor allocations
X-Git-Tag: v2.6.32-rc1~60^2^2~13^2~3
X-Git-Url: http://git.openpandora.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=162b96e63e518aa6ff029ce23de12d7f027483bf;p=pandora-kernel.git

ioat2,3: cacheline align software descriptor allocations

All the necessary fields for handling an ioat2,3 ring entry can fit into
one cacheline.  Move ->len prior to ->txd in struct ioat_ring_ent, and
move allocation of these entries to a hw-cache-aligned kmem cache to
reduce the number of cachelines dirtied for descriptor management.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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